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rev. pr d preliminary technical data preliminary technical data information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7621 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2003 16-bit, 1 lsb inl, 3 msps pulsar tm adc functional block diagram switched cap dac 16 control logic and calibration circuitry clock AD7621 d[15:0] busy rd cs ob/2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in+ in- pd reset serial port parallel interface cnvst pdbuf refbufin warp impulse byteswap pdref ref temp ser/par features 16 bits resolution with no missing codes no pipeline delay ( sar architecture ) differential input range: v ref (v ref up to 2.5v) throughput: 3 msps (wideband warp and warp mode) 2 msps (normal mode) 1.25 msps (impulse mode) inl: 1 lsb max ( 0.0015% of full-scale) s/(n+d): 90 db typ @ 100 khz ( v ref = 2.5v ) thd: ?100 db typ @ 100 khz parallel (16 or 8bits bus) and serial 5v/3.3v/2.5v interface spi/qspi/microwire/dsp compatible on-board low drift reference with buffer and temperature sensor single 2.5 v supply operation power dissipation: 100 mw typ @ 3 msps power-down mode package: 48-lead quad flat pack (lqfp) 48-lead frame chip scale package (lfcsp) speed upgrade of the ad7677 applications medical instruments high speed data acquisition communications instrumentation spectrum analysis ate general description the AD7621 is a 16-bit, 3 msps, charge redistribution sar, fully differential analog-to-digital converter that operates from a single 2.5 v power supply. the part contains a high-speed 16-bit sampling adc, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. it features a very high sampling rate mode (wideband warp) for undersampling applications and, for asyn- chronous conversion rate applications, a fast mode (normal) and, for low power applications, a reduced power mode (impulse) where the power is scaled with the throughput. it is available in a 48-lead lqfp or a 48-lead lfcsp with operation specified from ?40c to +85c. product highlights 1. high resolution and fast throughput the AD7621 is a 3 msps, charge redistribution, 16-bit sar adc ( no latency ). 2. excellent accuracy the AD7621 has a maximum integral nonlinearity of 1 lsb with no missing 16-bit code. 3. single-supply operation the AD7621 operates from a single 2.5 v supply and typically dissi pates only 100 mw. in impulse mode, its power dissi pation decreases with the throughput and it features a power-down mode. 5. serial or parallel interface versatile parallel (16 or 8 bits bus) or 2-wire serial interface arrangement compatible with either 2.5v, 3.3v or 5 v logic. pseudo ad7651 ad7650 / 52 ad7653 differential ad7660 / 61 ad7664 / 66 ad7667 true bipolar ad7663 ad7665 ad7671 true ad7675 ad7676 ad7677 AD7621 differential 18 bit ad7678 ad7679 ad7674 multichannel / ad7654 ad7655 simultaneous type / ksps 100 - 250 500 - 570 800 - 1000 >1000 pulsar selection
rev. pr d preliminary technical data ?2? AD7621?specifications (?40 c to +85 c, v ref = avdd, avdd = dvdd = ovdd = 2.5 v, unless otherwise noted. ) ) ) ) ) parameter conditions min typ max unit resolution 16 bits analog input voltage range v in+ ? v in- -v ref +v ref v operating input voltage v in+, v in- to agnd ?0.1 avdd v analog input cmrr f in = tbd khz tbd db input current tbd msps throughput t b d a input impedance see analog input section throughput speed complete cycle in wideband warp mode 3 3 3 n s throughput rate in wideband warp mode 0 . 1 3 msps throughput rate in warp mode 0.001 3 msps time between conversions in warp mode 1 ms complete cycle in normal mode 500 ns throughput rate in normal mode 0 2 msps complete cycle in impulse mode 800 ns throughput rate in impulse mode 0 1.25 msps dc accuracy integral linearity error ? 1 1 + 1 lsb 1 differential linearity error ? 1 + 1 l s b no missing codes 1 6 bits transition noise v ref = avdd 0.7 l s b gain error, t min to t max 2 tbd % of fsr gain error temperature drift tbd ppm/c zero error, t min to t max 2 tbd tbd lsb zero error tem perature drift tbd ppm/c power supply sensitivity avdd = 2.5v 5% tbd lsb ac accuracy signal-to-noise f in = 100 khz, v ref =avdd 88 90 db 3 v ref =2.048v 88.3 db spurious free dynamic range f in = 100 khz 100 d b total harmonic distortion f in = 100 khz ?100 db signal-to-(noise+distortion) f in = 100 khz, 9 0 d b f in = 100 khz,?60 db input 30 db ?3 db input bandwidth 5 0 m h z sampling dynamics aperture delay 1ns aperture jitter tbd ps rms transient response full-scale step 5 0 ns overvoltage recovery 50 ns reference external reference voltage range r e f t b d 2.048 avdd v ref current drain 3 msps throughput t b d a ref voltage with reference buffer refbufin=1.2v 2 2.048 2.1 v reference buffer input voltage refbufin tbd 1.2 tbd v refbufin input current ? 1 + 1 a internal reference internal reference voltage @ 25 c tbd 1.2 tbd v internal reference temp drift ?40 c to +85 c t b d ppm/ c internal reference temp drift 0 c to +70 c t b d ppm/ c refbufin line regulation avdd = 2.5v 5% t b d ppm/v refbufin output resistance 16 k power supply rejection @ tbd khz t b d d b turn-on settling time t b d s long-term stability 1,000 hours t b d ppm hysterisis tbd ppm refbufin output resistance t b d k temperature pin voltage output @ 25 c 313 m v temperature sensitivity 1 mv/ c temp pin output resistance 4.3 k
rev. pr d preliminary technical data AD7621 ?3? parameter conditions min typ max unit digital inputs logic levels v il ?0.3 +0.6 v v ih +1.7 5.25 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format parallel or serial 16-bits pipeline delay conversion results available immediately after completed conversion v ol i sink = 500 a 0 . 4 v v oh i source = ?500 a ovdd ? 0.3 v power supplies specified performance avdd 2.37 2.5 2.63 v dvdd 2.37 2.5 2.63 v ovdd 2.3 3.6 v operating current 4 3 msps throughput avdd 15 ma dvdd 5 4.5 ma ovdd 5 130 a power dissipation 5 pdbuf high @ 3 msps 4 100 tbd mw pdbuf low @ 3 msps 4 108 tbd mw pdbuf high @ 1.25 msps 6 tbd tbd mw pdbuf low @ 1.25 msps 6 tbd tbd mw in power-down mode 7 tbd tbd w temperature range 8 specified performance t min to t max ?40 +85 c notes 1 lsb means least significant bit. with the 2.5 v input range, one lsb is 76.294 v. 2 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale unless o therwise specified. 4 in warp mode. 5 tested in parallel reading mode. 6 in impulse mode. 7 with all digital inputs forced to dvdd or dgnd respectively. 8 contact factory for extended temperature range. specifications subject to change without notice. timing specifications symbol min typ max unit refer to figures 12 and 13 convert pulsewidth t 1 5ns time between conversions t 2 333/500/800 note 1 ns (warp mode/normal mode/impulse mode) cnvst low to busy high delay t 3 30 ns busy high all modes except in master serial read after t 4 263/400/750 ns convert (warp mode/normal mode/impulse mode) aperture delay t 5 1ns end of conversion to busy low delay t 6 10 ns conversion time (warp mode/normal mode/impulse mode) t 7 263/400/750 ns acquisition time (warp mode/normal mode/impulse mode) t 8 70/100/50 ns reset pulsewidth t 9 10 ns refer to figures 14, 15, and 16 (parallel interface modes) cnvst low to data valid delay t 10 263/400/750 ns (warp mode/normal mode/impulse mode) data valid to busy low delay t 11 20 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 215ns (?40 c to +85 c, avdd = dvdd = 2.5 v, ovdd = 2.3 v to 3.6 v, unless otherwise noted.)
rev. pr d preliminary technical data AD7621 ?4? table i. serial clock timings in master read after convert divsclk[1] 0011unit divsclk[0] 0101 sync to sclk first edge delay minimum t 18 tbd tbd tbd tbd ns internal sclk period minimum t 19 tbd tbd tbd tbd ns internal sclk period maximum t 19 tbd tbd tbd tbd ns internal sclk high minimum t 20 tbd tbd tbd tbd ns internal sclk low minimum t 21 tbd tbd tbd tbd ns sdout valid setup time minimum t 22 tbd tbd tbd tbd ns sdout valid hold time minimum t 23 tbd tbd tbd tbd ns sclk last edge to sync delay minimum t 24 tbd tbd tbd tbd ns busy high width maximum (warp) t 28 tbd tbd tbd tbd ns busy high width maximum (normal) t 28 tbd tbd tbd tbd ns busy high width maximum (impulse) t 28 tbd tbd tbd tbd ns refer to figures 18 and 19 (master serial interface modes) 2 cs low to sync valid delay t 14 tbd ns cs low to internal sclk valid delay t 15 tbd ns cs low to sdout delay t 16 tbd ns cnvst low to sync delay t 17 tbd ns (warp mode/normal mode/impulse mode) sync asserted to sclk first edge delay 3 t 18 tbd ns internal sclk period 3 t 19 tbd tbd ns internal sclk high 3 t 20 tbd ns internal sclk low 3 t 21 tbd ns sdout valid setup time 3 t 22 tbd ns sdout valid hold time 3 t 23 tbd ns sclk last edge to sync delay 3 t 24 tbd cs high to sync hi-z t 25 tbd ns cs high to internal sclk hi-z t 26 tbd ns cs high to sdout hi-z t 27 tbd ns busy high in master serial read after convert 3 t 28 see table i ns cnvst low to sync asserted delay t 29 tbd ns (warp mode/normal mode/impulse mode) sync deasserted to busy low delay t 30 tbd ns refer to figures 20 and 22 (slave serial interface modes) external sclk setup time t 31 5ns external sclk active edge to sdout delay t 32 27ns sdin setup time t 33 tbd ns sdin hold time t 34 tbd ns external sclk period t 35 12.5 ns external sclk high t 36 5ns external sclk low t 37 5ns notes 1 in warp mode only, the maximum time between conversions is 1ms; otherwise, there is no required maximum time. 2 in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 3 in serial master read during convert mode. see table i for serial master read after convert mode. specifications subject to change without notice. symbol min typ max unit timing specifications (continued)
rev. pr d preliminary technical data AD7621 ?5? warning ing! esd sensitive device absolute maximum ratings 1 analog inputs in+ 2 , in- 2 , ref, refbufin, temp, refgnd to agnd . . . . . . . . . . avdd + 0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd . . . . . . . . . . . . . . . . . . . -0.3v to +2.7 v ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +3.8 v digital inputs . . . . . . . . . . . . . . . . . . . . . . ?0.3 v to 5.5v internal power dissipation 3 . . . . . . . . . . . . . . . . 700 mw internal power dissipation 4 . . . . . . . . . . . . . . . . . . . 2.5w junction temperature . . . . . . . . . . . . . . . . . . . . . . . . 150c storage temperature range . . . . . . . . . ?65c to +150c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: = = = () + () + () + ( ) + ( ) ? * * figure 1. load circuit for digital interface timing, sdout, sync, sclk outputs, c l = 10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay figure 2. voltage reference levels for timing
rev. pr d preliminary technical data AD7621 ?6? pin configuration 48-lead lqfp and 48-lead lfcsp (st-48 and cp-48) 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd nc byteswap ob/2c nc = no connect ser/par d0 d1 d2/divsclk[0] busy d15 d14 d13 AD7621 d3/divsclk[1] d12 d4/ext/int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror pdbuf pdref refbufin temp avdd in+ agnd agnd nc in- refgnd ref impulse warp
rev. pr d preliminary technical data AD7621 ?7? pin function descriptions pin no. mnemonic type description 1, 41, 42 agnd p an alog power ground pin. 2, 44 avdd p input analog power pins. nominally 2.5 v. 3, 40 n c no connect. 4 byteswap di parallel mode selection (8-bit/16-bit). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d[7:0]. 5 ob/ 2c di straight binary/binary two?s complement. when ob/ 2c is high, the digital output is straight binary; when low, the msb is inverted resulting in a two?s complement output from its internal shift register. 6 warp di conversion mode selection. when high and impulse low, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. when low, full accuracy is maintained independent of the minimum conversion rate. 7 impulse di conversion mode selection. when high and warp low, this input selects a reduced power mode. in this mode, the power dissipation is approximately proportional to the sampling rate. 8 ser/ par d i serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface is selected and some bits of the data bus are used as a serial port. 9, 10 d[0:1] d o bit 0 and bit 1 of the parallel port data output bus. when ser/ par is high, these outputs are in high impedance. 11,12 d[2:3]or di/o when ser/ par is low, these pins are bit 2 and bit 3 of the parallel port data output bus. divsclk[0:1] when ser/ par is high , ext/ int is low, and rdc/sdin is low, which is serial master read after convert, these inputs, part of the serial port, are used to slow down if desired the internal serial clock which clocks the data output. in other serial modes, these pins are high impedance outputs. 13 d 4 di/o when ser/ par is low, this output is used as bit 4 of the parallel port data output bus. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. with ext/ int tied low, the internal clock is selected on sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input. 14 d 5 di/o when ser/ par is low, this output is used as bit 5 of the parallel port data output bus. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. when low, sync is active high. when high, sync is active low. 15 d 6 di/o when ser/ par is low, this output is used as bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both master and slave mode. 16 d 7 di/o when ser/ par is low, this output is used as bit 7 of the parallel port data output bus. or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 16 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the data is output on sdout during conversion. when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p i nput/output interface digital power. nominally at the same supply than the supply
rev. pr d preliminary technical data AD7621 ?8? of the host interface (2.5 v or 3 v). 19 dvdd p digital power. nominally at 2.5 v. 20 dgnd p digital power ground. 21 d 8 d o when ser/ par is low, this output is used as bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in an on-chip register. the AD7621 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on sclk falling edge and valid on the next rising edge. 22 d 9 di/o when ser/ par is low, this output is used as the bit 9 of the parallel port data output bus. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 d10 d o when ser/ par is low, this output is used as the bit 10 of the parallel port data output bus. or sync when ser/ par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and remains high while sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. 24 d11 d o when ser/ par is low, this output is used as the bit 11 of the parallel port data output bus. or rderror when ser/ par is high and when ext/ int is high, this output, part of the serial port, is used as a incomplete read error flag. in slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25?28 d[12:15] d o bit 12 to bit 15 of the parallel port data output bus. these pins are always outputs regard less of the interface mode. 29 busy d o busy output. transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p m ust be tied to digital ground. 31 rd d i read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs d i chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock. 33 reset di reset input. when set to a logic high, reset the AD7621. current conversion if any is aborted. if not used, this pin could be tied to dgnd. 34 p d d i power-down input. when set to a logic high, power consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst d i start conversion. a falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. in impulse mode (impulse high and warp low), if cnvst is held low when the acquisition phase ( t 8 ) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 36 agnd p m ust be tied to analog ground. 37 r e f ai reference input voltage and internal reference buffer output. apply an external reference on this pin if the internal reference buffer is not used. should be decoupled effectively with or without the internal buffer. 38 refgnd ai reference input analog ground. pin no. mnemonic type description
rev. pr d preliminary technical data AD7621 ?9? 39 in- ai differential negative analog input. 43 in+ ai differential negative analog input. 45 temp ao temperature sensor analog output typically 1mv/ c . 46 refbufin ai internal reference output and reference buffer input voltage. the internal reference buffer has a fixed gain. it outputs 2.048v typically when 1.2v is applied on this pin. 47 pdref di allows choice of internal or external voltage reference. when high, the internal reference is switched off and an external reference must been used. when low, the on-chip reference is turned on. 48 pdbuf di allows choice of buffering reference. when low, the buffer is selected. when high, the buffer is switched off. notes ai = analog input ai/o = bidirectional analog ao = analog output di = digital input di/o = bidirectional digital do = digital output p = power pin no. mnemonic type description
rev. pr d preliminary technical data AD7621 ?10? definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from ?negative full scale? through ?positive full scale?. the point used as ?negative full scale? occurs 1/2 lsb before the first code transition. ?positive full scale? is defined as a level 1 1/2 lsb be- yond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differ- ential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. gain error the first transition (from 000 . . . 00 to 000 . . . 01) should occur for an analog voltage 1/2 lsb above the nominal ? full scale (-2.047962 v for the 2.048v range). the last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (2.047886 v for the 2.048v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. zero error the zero error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms ampli- tude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following for- mula: enob = (s/[n+d] db ? 1.76)/6.02) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal to (noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition perfor- mance and is measured from the falling edge of the cnvst input to when the input signal is held for a con- version. transient response the time required for the AD7621 to achieve its rated accuracy after a full-scale step function is applied to its input. reference voltage temperature coefficient the change of the internal reference output voltage v over the operating temperature range and normalized by the output voltage at 25c, expressed in ppm/c. the equation follows: tcv ppm c vt vt vctt (/) () () ()( ) = ? ? () = v at 25c v(t 2 ) = v at temperature 2 v(t 1 ) = v at temperature 1 reference voltage long-term stability typical shift of output voltage at 25c on a sample of parts subjected to operation life test of 1000 hours at 125c: v ppm vt vt vt () () ( ) () = ? ( )= ( )= +++ v ppm vv c vc hys tc () () () = ? ()= =+ ++
rev. pr d preliminary technical data AD7621 ?11? typical performance characteristics- to be supplied tpc 1. integral nonlinearity vs. code to be supplied tpc 2. histogram of 131,072 conversions of a dc input at the code transition to be supplied tpc 3. typical positive inl distribution (tbd units) to be supplied tpc 4. differential nonlinearity vs. code to be supplied tpc 5. histogram of 131,072 conversions of a dc input at the code center to be supplied tpc 6. typical negative inl distribution (tbd units)
rev. pr d preliminary technical data AD7621 ?12? to be supplied tpc 7. typical inl and dnl vs temperature to be supplied tpc 8. fft to be supplied tpc 9. fft to be supplied tpc 10. typical inl and dnl vs sampling rate to be supplied tpc 11. snr, s/(n+d) and enob vs. frequency to be supplied tpc 12. thd, sfdr and harmonics vs. frequency
rev. pr d preliminary technical data AD7621 ?13? to be supplied tpc 13. snr, s/(n+d) and thd vs. input level to be supplied tpc 14. snr, s/(n+d) and enob vs temperature to be supplied tpc 15. thd, sfdr and harmonics vs temperature to be supplied tpc 16.operating current vs. sampling rate to be supplied tpc 17. power-down operating currents vs. temperature to be supplied tpc 18. positive and negative full scale, offset and refer- ence buffer gain vs. temperature
rev. pr d preliminary technical data AD7621 ?14? to be supplied tpc 19.positive and negative full scale, offset and reference buffer gain vs. supply . to be supplied tpc 20.typical delay vs. load capacitance cl to be supplied tpc 21.typical internal reference voltage vs. tem- perature to be supplied tpc 22. typical internal reference temperature drift distribution (tbd units) to be supplied tpc 23. typical internal reference hysterisis distribution (tbd units)
rev. pr d preliminary technical data AD7621 ?15? circuit information the AD7621 is a very fast, low-power, single-supply, precise 16-bit analog-to-digital converter (adc) using successive approximation architecture. the AD7621 features different modes to optimize perfor- mances according to the applications. in warp mode, the AD7621 is capable of converting 3,000,000 samples per second (3 msps). the AD7621 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipeline or latency, making it ideal for mul- tiple multiplexed channel applications. the AD7621 can be operated from a single 2.5 v supply and be interfaced to either 5 v or 3.3 v or 2.5 v digital logic. it is housed in a 48-lead lqfp or a tiny lfcsp packages that combines space savings and allows flexible configurations as either serial or parallel interface. the AD7621 is pin-to-pin-compatible with the ad7674. converter operation the AD7621 is a successive approximation analog-to- digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparator?s input are connected to agnd via sw + and sw - . all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sam- pling capacitors and acquire the analog signal on in+ and in- inputs. when the acquisition phase is complete and the cnvst input goes low, a conversion phase is initi- ated. when the conversion phase begins, sw + and sw - are opened first. the two capacitor arrays are then discon- sw + msb 32,768c 16,384c 4c 2c c c in+ lsb comp sw - control logic switches control busy output code cnvst ref refgnd msb 32,768c 16,384c 4c 2c c c in - lsb figure 3. adc simplified schematic nected from the inputs and connected to the refgnd input. therefore, the differential voltage between the in- puts in+ and in- captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd or ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4...v ref /65536). the control logic toggles these switches, starting with the msb first, in order to bring the comparator bac into a balanced condi- tion. after the completion of this process, the control logic generates the adc output code and brings busy output low. modes of operation the AD7621 features three modes of operations, arp, normal, and impulse. each of these modes is more suit- able for specific applications. the arp mode allows the fastest conversion rate up to 3 msps. however, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not eceed 1 ms. if the time be- tween two consecutive conver sions is longer than 1 ms, for instance, after power-up, the first con version result should be ignored. this mode maes the AD7621 ideal for appli- cations where fast sample rate are required. the normal mode is the fastest mode (2 msps) without any lim itation about the time between conversions. this mode maes the AD7621 ideal for asynchronous appli- cations such as data a cquisition systems, where both high accuracy and fast sample rate are required. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. the maimum throughput in this mode is 1.25 msps. this feature maes the AD7621 ideal for battery-powered applications.
rev. pr d preliminary technical data AD7621 ?16? 100nf 10 f 100nf 10 f avdd 10 f 100nf agnd dgnd dvdd ovdd ognd cnvst busy sdout sclk rd cs reset pd refbufin 10 d clock AD7621 c/ p/dsp serial port digital supply (2.5v or 3.3v) analog supply (2.5v) dvdd ob/2c note 6 dvdd in+ in- analog input- c c 1.2nf u2 15 note 5 note 3 50 note 4 ad8021 notes : note 1 : see voltage reference input section. note 2 : c ref is 10 f ceramic capacitor or low esr tantalum. ceramic size 1206 panasonic ecj-3xb0j106 is recommended. see voltage reference input section. note 3 : the ad8021 is recommended. see driver amplifier choice section. note 4 : see analog inputs section. note 5 : option. see power supply section. note 6 : optional low jitter cnvst. see conversion control section. analog input+ c c 1.2nf u1 15 note 3 note 4 ad8021 mode1 mode0 refgnd c ref ref 10 f note 2 pdbuf note 1 pdref c ref 100nf note 1 transfer functions using the ob/ 2c digital input, the AD7621 offers two output codings: straight binary and two?s complement. the ideal transfer characteristic for the AD7621 is shown in figure 4 and table iii. 000...000 000...001 000...010 111...101 111...110 111...111 adc code - straight binary analog input +fs-1.5 lsb +fs-1 lsb -fs+1 lsb -fs -fs+0.5 lsb figure 4. adc ideal transfer function table iii. output codes and ideal input voltages digital output code hea analog straight twos d escription input binary comple- v ref = 2.048v ment fsr 1 lsb 2.047924 v 3ffff 1 1ffff 1 fsr 2 lsb 2.047849 v 3fffe 1ffe midscale + 1 lsb 75.684v 20001 00001 midscale 0 v 20000 00000 midscale 1 lsb -75.684v 1ffff 3ffff fsr + 1 lsb -2.047924 v 00001 20001 fsr -2.048 v 00000 2 20000 2 notes 1 this is also the code for overrange analog input (v in+ v in- above v ref v refgnd ). 2 this is also the code for underrange analog input (v in+ v in- below -v ref + v refgnd ).
rev. pr d preliminary technical data AD7621 ?17? typical connection diagram figure 5 shows a typical connection diagram for the AD7621. different circuitry shown on this diagram are optional and are discussed below. analog inputs figure 6 shows a simplified analog input section of the AD7621. to be supplied figure 6. AD7621 simplified analog input. the diodes shown in figure 6 provide esd protection for the inputs. care must be taen to ensure that the analog input signal never eceeds the absolute ratings on these inputs. this will cause these diodes to become forward- biased and start conducting current. these diodes can handle a forward-biased current of 150 ma maimum. this condition could eventually occur when the input buffers (u1) or (u2) supplies are different from avdd. in such case, an input buffer with a short-circuit current limitation can be used to protect the part. this analog input structure is a true differential structure. by using these differential inputs, signals common to both inputs are reected as shown in figure 7 which represents the typical cmrr over frequency. to be supplied figure 7. analog input cmrr vs. frequency during the acquisition phase, for ac signals, the AD7621 behaves lie a one pole rc filter consisted of the equiva- lent resistance r+ , r- and c s . the resistors r+ and r- are typically tbd and are lumped component made up of some serial resistor and the on resistance of the switches. the capacitor c s is typically tbd pf and is mainly the adc sampling capacitor. this one pole filter with a typi- cal -3db cutoff frequency of 50 mhz reduces undesirable aliasing effect and limits the noise coming from the in- puts. because the input impedance of the AD7621 is very high, the AD7621 can be driven directly by a low impedance source without gain error. that allows to put, as shown in figure 5, an external one-pole rc filter between the out- put of the amplifier output and the adc analog inputs to even further improve the noise filtering done by the AD7621 analog input circuit. however, the source imped- ance has to be kept low because it affects the ac performances, especially the total harmonic distortion. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier choice although the AD7621 is easy to drive, the driver amplifier needs to meet at least the following requirements: the driver amplifier and the AD7621 analog input circuit have to be able together to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). in the amplifier?s datasheet, the settling at 0.1% or 0.01% is more commonly specified. it could significantly dif- fer from the settling time at 16 bit level and, therefore, it should be verified prior to the driver selection. the tiny op-amp ad8021 which combines ultra low noise and a high gain bandwidth meets this settling time requirement.
rev. pr d preliminary technical data AD7621 ?18? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the AD7621. the noise coming from the driver is filtered by the AD7621 analog input circuit one-pole low-pass filter made by r + , r - and c s . the snr degradation due to the ampli- fier is : snr log fne loss n = + () ? ? ? ? ? ? ? ? ? () ( ) () hz like the ad8021 and configured as a buffer, thus with a noise gain of +1, the snr degrades by only 0.17 db with the filter in figure 5, and 0.8 db without. the driver needs to have a thd performance suitable to that of the AD7621. the ad8021 meets these requirements and is usually appropriate for almost all applications. the ad8021 needs an external compensation capacitor of 10 pf. this capacitor should have good linearity as an npo ceramic or mica type. the ad8022 could also be used where dual version is needed and gain of 1 is used. single to differential driver for applications using unipolar analog signals, a single- ended to differential driver will allow for a differential input into the part. the schematic is shown in figure 8. this configuration, when provided an input signal of 0 to v ref , will produce a differential v ref with midscale at v ref /2. if the application can tolerate more noise, the ad8138, differential driver, can be used. 10pf u2 590 ad8021 analog input (unipolar 0 to 2.048v) 10pf u1 590 ad8021 in+ in- AD7621 1k 1k ref 10 f 15 15 100nf 1.2nf 1.2nf figure 8. single ended to differential driver circuit ( internal reference buffer used ) voltage reference the AD7621 allows the choice of either a very low tem- perature drift internal voltage reference or an eternal reference. unlie many adc with internal reference, the internal reference of the AD7621 provides ecellent performances and can be used in almost all applications. it is tempera- ture compensated to 1.2v tbd mv with a typical drift of tbd ppm/c, a typical long-term stability of tbd ppm and a typical hysterisis of tbd ppm. however, the advantages to use the eternal reference voltage directly are - the power saving of about 8m typical when the inter- nal reference and its buffer are powered down ( pdref and pdbuf high ) - the snr and dynamic range improvement of about 1.7 db resulting of the use of a reference voltage very close to the supply (2.5v) instead of a typical 2.048v reference when the internal buffer is used. to use the internal reference along with the internal buffer, pdref and pdbuf should both be lo. this will produce a voltage on refbufin of 1.2 v and the buffer will gain it up, resulting in a 2.048 v reference on ref pin. it is useful to decouple the refbufin pin with a 100 nf ceramic capacitor. the output impedance of the refbufin pin is 16 . thus, the 100 nf capacitor provides an rc filter for noise reduction. to use an eternal reference along with the internal buffer, pdref should be high and pdbuf should be low. this powers down the internal reference and allows for the 1.2 v reference to be applied to refbufin. to use an eternal reference directly on ref pin, pdref and pdbuf should both be high. it should be noted that the internal reference and internal buffer are independent of the power down (pd) pin of the part. furthermore, powering up the internal reference and internal buffer requires time due to the charge of the ref decoupling.
rev. pr d preliminary technical data AD7621 ?19? in both cases, the voltage reference input ref has a dy- namic input impedance and requires, therefore, an efficient decoupling between ref and refgnd inputs. when the internal reference buffer is used, this decoupling consists of a 10 f ceramic capacitor ( e.g. : panasonic ecj-3xb0j106 1206 size ). when external reference is used, the decoupling consists of a low esr 47 f tantalum capacitor connected to the ref and refgnd inputs with minimum parasitic induc- tance. temperature sensor the temp pin, which measures the temperature of the AD7621, can be used as shown in figure 9. the output of the temp pin is applied to one of the inputs of the ana- log switch (e.g. : adg779) and the adc itself is used to measure its own temperature. this configuration could be very useful to improve the calibration accuracy over the temperature range. to be supplied figure 9. use of the temperature sensor power supply the AD7621 uses three sets of power supply pins an ana- log 2.5 v supply avdd, a digital 2.5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic woring between 2.3 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the ana- log supply as shown in figure 5. the AD7621 is independent of power supply sequencing and thus free from supply voltage induced latchup. additionally, it is very insensitive to power supply variations over a wide frequency range as shown in figure 10. to be supplied figure 10. psrr vs. frequency poer dissipation vs. throughput in impulse mode, the AD7621 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low which allows a significant power saving when the conversion rate is reduced as shown in figure 11. this feature maes the AD7621 ideal for very low-power bat- tery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operat- ing digital supply currents even further, the d igital inputs need to be driven close to the power rails (i.e., dvdd and dgnd). to be supplied figure 11. power dissipation vs. sample rate
rev. pr d preliminary technical data AD7621 ?20? conversion control figure 12 shows the detailed timing diagrams of the con- version process. the AD7621 is controlled by the signal cnvst which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conversion is complete. the cnvst signal operates independently of cs and rd signals. cnvst busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acquire convert acquire convert figure 12. basic conversion timing although cnvst is a digital signal, it should be de- signed with this special care with fast, clean edges and levels, with minimum overshoot and undershoot or ring- ing. for applications where the snr is critical, the cnvst signal should have a very low jitter. some solutions to achieve that are to use a dedicated oscillator for cnvst generation or, at least, to clock it with a high frequency low jitter clock as shown in figure 5. in impulse mode, conversions can be automatically initi- ated. if cnvst is held low when busy is low, the AD7621 controls the acquisition phase and then automati- cally initiates a new conver sion. by keeping cnvst low, the AD7621 keeps the conver sion process running by itself. it should be noted that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the AD7621 could sometimes run slightly faster then the guaranteed limits in the impulse mode. this feature does not exist in warp or normal modes. t 9 t 8 reset data bus busy cnvst figure 13. reset timing digital interface the AD7621 has a versatile digital interface it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multipleed on the parallel data bus. the AD7621 digital interface also accommodates both 2.5v, 3.3v or 5v l ogic with either ovdd at 2.5v or 3.3v. ovdd defines the logic high out- put voltage. in most applications, the ovdd supply pin of the AD7621 is connected to the host system interface 2.5v or 3.3v digital supply. finally, by using the ob/ 2c input pin, both two?s complement or straight binary coding can be used. the two signals cs and rd control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each AD7621 in multi-circuits applications and is held low in a single AD7621 design. rd is generally used to enable the conversion result on the data bus. t 1 t 3 t 4 t 11 cnvst busy data bus cs = rd = 0 t 10 previous conversion data new data figure 14. master parallel data timing for reading (continuous read)
rev. pr d preliminary technical data AD7621 ?21? parallel interface the AD7621 is configured to use the parallel interface with either a 16-bit or 8-bit bus width. the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in figure 15 and figure 16. when the data is read during the conversion, however, it is rec- ommended that it is read only during the first half of the conversion phase. that avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion busy data bus cs rd t 12 t 13 figure 15. slave parallel data timing for reading (read after convert) t 1 t 3 t 4 cs = 0 cnvst, rd busy previous conversion t 12 t 13 data bus figure 16. slave parallel data timing for reading (read during convert) cs a0, a1 pins d158 hi- high byte lo byte hi- hi- high byte lo byte hi- t 12 t 12 t 13 pins d70 rd figure 17. 8-bit and 16-bit parallel interface t 3 busy cs, rd cnvst sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 123 16 d15 d14 d2 d1 d0 et/int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 15 14 figure 18. master serial data timing for reading (read after convert)
rev. pr d preliminary technical data AD7621 ?22? serial interface the AD7621 is configured to use the serial interface when ser/ par is held high. the AD7621 outputs 16 bits of data, msb first, on the sdout pin. this data is syn- chronized with the 16 clock pulses provided on sclk pin. the output data is valid on both the rising and falling edge of the data clock. that allows a fast serial interface speed by using the same clock edge to output the data from the adc and to sample the previous bit by the digi- tal host. master serial interface internal clock the AD7621 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the AD7621 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. depending on rdc/sdin input, the data can be read after each conversion or during the following conversion. figure 18 and figure 19 show the detailed timing dia- grams of these two modes. usually, because the AD7621 is used with a fast through- put, the mode master, read during conversion is the most recommended serial mode when it can be used. in read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimize potential feedthrough between digital activity and the critical con- version decisions. in read-after-conversion mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer busy width. to accomodate slow digital hosts, the serial clock can be slowed down by using divsclk. slave serial interface external clock the AD7621 is configured to accept an externally sup- plied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several meth- ods can be used to read the data. the external serial clock is gated by cs . when cs and rd are both low, the data can be read afte r each conversion or during the following conversion. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figure 20 and figure 22 show the detailed timing diagrams of these meth ods. while the AD7621 is performing a bit decision, it is impor- tant that voltage transients not occur on digital input/output pins or deg radation of the conversion result could occur. this is particularly important during the second half of the conversion phase be cause the AD7621 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when busy is low or, more importantly, that it does not transition dur- ing the latter half of busy high. ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 141516 t 18 busy cs, rd cnvst sync sclk sdout figure 19. master serial data timing for reading (read previous conversion during convert)
rev. pr d preliminary technical data AD7621 ?23? external discontinuous clock data read after con- version though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 20 shows the detailed timing dia- grams of this method. after a conversion is complete, indicated by busy returning low, the result of this con- version can be read while both cs and rd are low. the data is shifted out, msb first, with 16 clock pulses and is valid on both rising and falling edge of the clock. among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is to be able to read the data at any speed up to 80 mhz which accommodates both slow digital host interface and the fastest serial reading. finally, in this mode only, the AD7621 provides a ?daisy-chain? feature using the rdc/sdin input pin for cascading multiple converters together. this feature is useful for reducing component count and wiring connec- tions when desired as, for instance, in isolated multiconverter applications. an example of the concatenation of two devices is shown in figure 21. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the edge of sclk oppo- site to the one used to shift out the data on sdout. hence, the msb of the ?upstream? converter just follows the lsb of the ?downstream? converter on the next sclk cycle. sclk sdout d15 d14 d1 d0 d13 x15 x14 x13 x 1 x0 y15 y14 cs busy sdin ext/int = 1 invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 t 34 x15 x14 x 12 18 rd = 0 17 16 15 3 figure 20. slave serial data timing for reading (read after convert) sdout cs sclk d1 d0 d15 d14 d15 12 16 t 3 t 35 t 36 t 37 t 31 t 32 t 16 cnvst busy et/int = 1 invsclk = 0 rd =0 315 4 figure 22. slave serial data timing for reading (read previous conversion during convert)
rev. pr d preliminary technical data AD7621 ?24? cnvst cs sclk sdout rdc/sdin busy busy data out AD7621 #1 (downstream) busy out cnvst cs sclk AD7621 #2 (upstream) rdc/sdin sdout sclk in cs in cnvst in figure 21. two AD7621s in a daisy-chain configuration eternal cloc data read during conversion figure 22 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are both low, the result of the previous conversion can be read. the data is shifted out, msb first, with 16 clock pulses and is valid on both rising and falling edge of the clock. the 16 b its have to be read before the current con- version is complete. if that is not done, rderror is pulsed high and can be used to interrupt the host inter- face to prevent incomplete data reading. there is no ?daisy chain? feature in this mode and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock of is recommended to ensure that all the bits are read during the first half of the conversion phase. it is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. microprocessor interfacing the AD7621 is ideally suited for traditional dc measure- ment applications supporting a microprocessor, and ac signal processing applications interfacing to a digital sig- nal processor. the AD7621 is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the AD7621 to prevent digital noise from coupling into the adc. the following section illustrates the use of the AD7621 with an spi equipped dsp, the adsp-219x. spi interface (adsp-219x) figure 22 shows an interface diagram between the AD7621 and an spi-equipped dsp, adsp219x. to accommodate the slower speed of the dsp, the ad 7621 acts as a slave device and data must be read after conver- sion. this mode also allows the ?daisy chain? feature. the convert command could be initiated in response to an internal timer interrupt. the reading process could be initiated in response to the end-of-conver sion signal (busy going low) using an interrupt line of the dsp. the serial peripheral interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polar- ity bit (cpol) = 0, clock phase bit (cpha) = 1 and spi interrupt enable (timod) =00 by writing to the spi control register (spicltx). it should be noted that to meet all timing requirements, the spi clock should be limited to 17mbits/s which allow to read an adc result in about 1.1 s. when higher sampling rate is desired, it is recomended to use one of the parallel interface mode with the adsp-219x. spixsel (pfx) adsp-219x* cnvst AD7621* cs misox sckx pfx or tfsx sdout sclk invsclk ext/int dvdd *additional pins omitted for clarity ser/par rd pfx busy figure 23. interfacing the AD7621 to spi interface
rev. pr d preliminary technical data AD7621 ?25? application hints layout the AD7621 has very good immunity to noise on the power supplies. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the AD7621 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of g round planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably under- neath the AD7621, or, at least, as close as possible to the AD7621. if the AD7621 is in a system where multiple devices r equire analog to digital ground connections, the connection should still be made at one point only, a star ground point, w hich should be established as close as possible to the AD7621. it is recommended to avoid running digital lines under the device as t hese will couple noise onto the die. the analog ground plane s hould be allowed to run under the AD7621 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the AD7621 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decou- pling is also important to lower the supplies impedance presented to the AD7621 and reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typi- cally 100 nf, should be placed on each power supplies pins avdd, dvdd and ovdd close to, and ideally right up against these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the dvdd supply of the AD7621 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, it is recommended if no sepa- rate supply available, to connect the dvdd digital supply to the analog supply avdd through an rc filter as shown in figure 5, and connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. when dvdd is powered from the system sup- ply, it is useful to insert a bead to further reduce high-frequency spikes. the AD7621 has four different ground pins; refgnd, agnd, dgnd, and ognd. refgnd senses the refer- ence voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog sig- nals are referenced. this ground must be con nected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane de pend- ing on the configuration. ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is important. the decoupling capacitor should be close to the adc and connected with short and large traces to minimize parasitic inductances. evaluating the AD7621 performance a recommended layout for the AD7621 is outlined in the documentation of the eval-AD7621-cb , evaluation board for the AD7621. the evaluation board package includes a fu lly assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval control brd3.
rev. pr d preliminary technical data AD7621 ?26? outline dimensions dimensions shown in inches and (mm). 48-lead quad flatpack (lqfp) (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 (0.05) 7 0 0.057 (1.45) 0.053 (1.35) 48-lead frame chip scale package (lfcsp) (cp-48) pin 1 indicator top view 0.266 (6.75) bsc sq 0.276 (7.0) bsc sq 1 48 12 13 37 36 24 25 bottom view 0.215 (5.45) 0.209 (5.30) sq 0.203 (5.15) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) bsc 0.031 (0.80) max 0.026 (0.65) nom 12 ? max 0.039 (1.00) max 0.033 (0.85) nom 0.008 (0.20) ref 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) controlling dimensions are in millimeters paddle connected to agnd ( this connection is not require d to meet electrical performances )

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